Processing a semiconductor wafer

ABSTRACT

A semiconductor wafer processing system for processing a semiconductor wafer is presented. The semiconductor wafer processing system comprises: a trench production apparatus configured to produce trenches in the semiconductor wafer, the trenches being arranged next to each other along a first lateral direction (X); a trench filling apparatus configured to epitaxially fill the trenches with a doped semiconductor material; and a controller operatively coupled to at least one of the trench production apparatus and the trench filling apparatus, wherein the controller is configured to control at least one of the trench production apparatus and the trench filling apparatus in dependence of a parameter, the parameter being indicative of at least one of a variation of dopant concentrations of the doped semiconductor material along the first lateral direction (X) that is to be expected when carrying out the epitaxially filling and a deviation of an expected average of the dopant concentrations from a predetermined nominal value.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to German Application Serial No.102015208794.8 filed May 12, 2015 and entitled “Processing aSemconductor Wafer.”

TECHNICAL FIELD

This specification refers to embodiments of a method of processing asemiconductor wafer, embodiments of a semiconductor wafer processingsystem and to embodiments of a semiconductor wafer. In particular, thisspecification refers to embodiments of a semiconductor wafer based onsilicon carbide and to embodiments of a method and a system forprocessing such semiconductor wafer.

BACKGROUND

Many functions of modern devices in automotive, consumer and industrialapplications, such as converting electrical energy and driving anelectric motor or an electric machine, rely on semiconductor devices.For example, Insulated Gate Bipolar Transistors (IGBTs), Metal OxideSemiconductor Field Effect Transistors (MOSFETs) and diodes, to name afew, have been used for various applications including, but not limitedto switches in power supplies and power converters.

Such power supplies or, respectively, power converters shall usuallyexhibit a high degree of efficiency. To this end, semiconductor deviceshave been proposed that exhibit a so-called compensation structure,wherein such devices are also referred to as “superjunction” or“CoolMOS”™ devices. Such compensation structure may lead to a reductionof the on-state resistance of the semiconductor device.

SUMMARY

According to an embodiment, a method of processing a semiconductor waferis presented. The method includes epitaxially filling of trenches of thesemiconductor wafer with a doped semiconductor material, wherein thetrenches are arranged next to each other along a first lateraldirection. The method further comprises: Determining a parameterindicative of at least one of a variation of dopant concentrations ofthe doped semiconductor material along the first lateral direction thatis to be expected when carrying out the epitaxially filling and adeviation of an expected average of the dopant concentrations from apredetermined nominal value; and carrying out at least one subsequentprocessing step in dependence of the parameter.

According to a further embodiment, a semiconductor wafer processingsystem for processing a semiconductor wafer is presented. The systemcomprises: a trench production apparatus configured to produce trenchesin the semiconductor wafer, the trenches being arranged next to eachother along a first lateral direction; a trench filling apparatusconfigured to epitaxially fill the trenches with a doped semiconductormaterial; and a controller operatively coupled to at least one of thetrench production apparatus and the trench filling apparatus, whereinthe controller is configured to control at least one of the trenchproduction apparatus and the trench filling apparatus in dependence of aparameter, the parameter being indicative of at least one of a variationof dopant concentrations of the doped semiconductor material along thefirst lateral direction that is to be expected when carrying out theepitaxially filling and a deviation of an expected average of the dopantconcentrations from a predetermined nominal value.

According to another embodiment, a semiconductor wafer comprising anactive region and a wafer edge region surrounding the active region ispresented. The active region includes a number of transistor cells beingconfigured to carry a load current by means of a semiconductor driftregion arranged within the active region. The semiconductor waferfurther comprises: trenches extending into the semiconductor driftregion along a vertical extension direction, the trenches being arrangednext to each other along a first lateral direction and being filled witha doped semiconductor material, the doped semiconductor materialexhibiting a band gap greater than the band gap of silicon, wherein, foreach pair of adjacent trenches, a volume integral of the dopantconcentration of the doped semiconductor material filled in a firsttrench of the pair deviates from a corresponding volume integral of thedopant concentration of the doped semiconductor material filled in asecond trench of the pair by no more than 10%.

Those skilled in the art will recognize additional features andadvantages upon reading the following detailed description, and uponviewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The parts in the figures are not necessarily to scale, instead emphasisbeing placed upon illustrating principles of the invention. Moreover, inthe figures, like reference numerals designate corresponding parts. Inthe drawings:

FIG. 1 schematically illustrates a section of a horizontal projection ofa semiconductor wafer according to one or more embodiments;

FIG. 2A-C schematically illustrate sections of a vertical cross-sectionof a semiconductor wafer during some steps of a method of processingsuch semiconductor wafer according to one or more embodiments;

FIG. 3 schematically illustrates a block diagram of components of asemiconductor wafer processing system according to one or moreembodiments; and

FIG. 4 schematically illustrates an exemplary distribution of volumeintegrals of dopant concentrations according to one or more embodiments.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings which form a part hereof and in which are shown byway of illustration specific embodiments in which the invention may bepracticed.

In this regard, directional terminology, such as “top”, “bottom”,“below”, “front”, “behind”, “back”, “leading”, “trailing”, etc., may beused with reference to the orientation of the figures being described.Because parts of embodiments can be positioned in a number of differentorientations, the directional terminology is used for purposes ofillustration and is in no way limiting. It is to be understood thatother embodiments may be utilized and structural or logical changes maybe made without departing from the scope of the present invention. Thefollowing detailed description, therefore, is not to be taken in alimiting sense, and the scope of the present invention is defined by theappended claims.

Reference will now be made in detail to various embodiments, one or moreexamples of which are illustrated in the figures. Each example isprovided by way of explanation, and is not meant as a limitation of theinvention. For example, features illustrated or described as part of oneembodiment can be used on or in conjunction with other embodiments toyield yet a further embodiment. It is intended that the presentinvention includes such modifications and variations. The examples aredescribed using specific language which should not be construed aslimiting the scope of the appended claims. The drawings are not scaledand are for illustrative purposes only. For clarity, the same elementsor manufacturing steps have been designated by the same references inthe different drawings if not stated otherwise.

The term “horizontal” as used in this specification intends to describean orientation substantially parallel to a horizontal surface of asemiconductor substrate or of a semiconductor region. This can be forinstance the surface of a semiconductor wafer or a die. For example,both the first lateral direction X and the second lateral direction Ymentioned below can be horizontal directions, wherein the first lateraldirection X and the second lateral direction Y may be perpendicular toeach other.

The term “vertical” as used in this specification intends to describe anorientation which is substantially arranged perpendicular to thehorizontal surface, i.e., parallel to the normal direction of thesurface of the semiconductor wafer. For example, the extension directionZ mentioned below may be a vertical direction that is perpendicular toboth the first lateral direction X and the second lateral direction Y.

In this specification, n-doped is referred to as “first conductivitytype” while p-doped is referred to as “second conductivity type”.Alternatively, opposite doping relations can be employed so that thefirst conductivity type can be p-doped and the second conductivity typecan be n-doped. Further, within this specification, the term “dopantconcentration” may refer to an integral dopant concentration or,respectively, to a mean dopant concentration or to a sheet chargecarrier concentration of a specific semiconductor region orsemiconductor zone, such as a semiconductor region within a trench.Thus, e.g., a statement saying that a specific semiconductor regionexhibits a certain dopant concentration that is higher or lower ascompared to a dopant concentration of another semiconductor region mayindicate that the respective mean dopant concentrations of thesemiconductor regions differ from each other.

In the context of the present specification, the terms “in Ohmiccontact”, “in electric contact”, “in Ohmic connection”, and“electrically connected” intend to describe that there is a low Ohmicelectric connection or low Ohmic current path between two regions,sections, zones, portions or parts of a semiconductor device or betweendifferent terminals of one or more devices or between a terminal or ametallization or an electrode and a portion or part of a semiconductordevice. Further, in the context of the present specification, the term“in contact” intends to describe that there is a direct physicalconnection between two elements of the respective semiconductor device;e.g., a transition between two elements being in contact with each othermay not include a further intermediate element or the like.

Specific embodiments described in this specification pertain to, withoutbeing limited thereto, a semiconductor wafer including a number of powersemiconductor devices, e.g., monolithically integrated diode ortransistor cells, such as monolithically integrated IGBT cells,monolithically integrated MOS Gated Diode (MGD) cells, or monolithicallyintegrated MOSFET cells and/or derivatives thereof that may be usedwithin a power converter or a power supply.

The term “power semiconductor device” as used in this specificationintends to describe a semiconductor device on a single chip with highvoltage blocking and/or high current-carrying capabilities. In otherwords, such power semiconductor device is intended for high current,typically in the Ampere range, e.g., up to several ten or hundredAmpere, and/or high voltages, typically above 30 V, more typically 100V, or even more than 600 V, and above.

FIG. 1 schematically illustrates a section of a horizontal projection ofa semiconductor wafer 1 according to one or more embodiments. FIG. 2Cschematically and exemplary illustrates a section of a verticalcross-section of the semiconductor device 1 in accordance with one ormore embodiments. In the following, reference will be made to both FIG.1 and FIG. 2C.

For example, the semiconductor wafer 1 exhibits a diameter of somemillimeters, such as a diameter of 100 mm, of 150 mm, of 200 mm, of 300mm or of 450 mm or of more than 450 mm. The semiconductor wafer 1 maycomprise an active region 15 and a wafer edge region 16 that surroundsthe active region 15 and that may be a non-active region.

For example, the active region 15 includes a number of transistor cells(not illustrated in the figures) that are configured to carry a loadcurrent by means of a semiconductor drift region 13 of the semiconductorwafer 1. The semiconductor drift region 13 can be arranged within theactive region 15 and may exhibit a total extension along a verticalextension direction, i.e., a depth of at least 5 μm. For example, thewafer edge region 16 does not include any transistor cells that areconfigured to carry a load current. Each of the transistor cells maycomprise at least one gate electrode, which can be, e.g., realized as atrench gate electrode extending into the semiconductor drift region 13or, respectively, as a planar gate electrode being arranged above thesemiconductor drift region 13.

The semiconductor wafer 1 further comprises a number of trenches 10 thatextend into the semiconductor drift region 13 along the verticalextension direction Z. In FIG. 1, thirteen trenches 10 a to 10 m areschematically illustrated by way of example. It goes without saying thatthe semiconductor wafer 1 may certainly comprise more or less thanthirteen trenches. For example, the semiconductor wafer comprises atleast 10⁵ trenches 10. In FIG. 2C, only five of such trenches 10 a to 10e are schematically illustrated. The trenches 10 can be arranged next toeach other along a first lateral direction X and can each be filled witha doped semiconductor material 11.

For example, the trenches 10 each exhibit the same total extension alongthe vertical extension direction Z. In other words, the trenches 10 mayall exhibit the same trench depth. For example, the trench depths areeach within the range of 0.2 μm to

For example, the trench depths (i.e., the total extensions along thevertical extension directions) are each within the range of 1 μm to 10μm. Further, the trenches 10 may each exhibit the same total extensionalong the second lateral direction Y. In other words, the trenches 10may all exhibit the same trench length. The distance (also referred toas “pitch”) along the first lateral direction X between every twoadjacent trenches of the trenches 10 may amount to less than 10 μm, toless than 3 μm or even to less than 1 μm.

The doped semiconductor material 11 may exhibit a band gap greater thanthe band gap of silicon. For example, the doped semiconductor material11 is doped silicon carbide (SiC). Further, the band gap of the dopedsemiconductor material 11 can amount to at least 2 eV.

In an embodiment, the semiconductor drift region 13 is made of asemiconductor material comprising dopants of the first conductivitytype, and the doped semiconductor material 11 comprises dopants of thesecond conductivity type. For example, the semiconductor drift region 13is an n-doped region and the semiconductor material 11 is p-doped. Forexample, the dopant concentration of the semiconductor drift region 13is greater than 10¹³/cm³, and the dopant concentration of the dopedsemiconductor material 11 filled within each of the trenches 10 isgreater than 10¹⁵/cm³. In an embodiment, the dopant concentration of thedoped semiconductor material 11, which can be p-doped, is at least twiceas large as the dopant concentration of the semiconductor drift region13, which can be n-doped. For example, the latter relations of thedopant types and the dopant concentrations may be appropriate in theevent that the doped semiconductor material 11 filled into the trenches10 is used for compensation purposes (compensation trenches), e.g., forforming a superjunction structure.

Further, the doped semiconductor material 11 may be in contact with thesemiconductor drift region 13.

For example, also the semiconductor drift region 13 can be made of asemiconductor material that exhibits a band gap greater than the bandgap of silicon. For example, the semiconductor drift region 13 is madeof doped silicon carbide (SiC).

In an embodiment, each of the transistor cells of the semiconductorwafer 1 may exhibit a compensation structure (also referred to as“superjunction” structure) formed at least by means of the trenches 10filled with a doped semiconductor material 11. In other words, thetrenches 10 may form a compensation structure for compensating for thedopants of the semiconductor drift region 13.

Further, for each pair of adjacent trenches, such as trenches 10 a and10 b, or trenches 10 b and 10 c, or trenches 10 l and 10 m and so on, avolume integral of the dopant concentration of the doped semiconductormaterial 11 filled in a first trench of the respective pair deviatesfrom a corresponding volume integral of the dopant concentration of thedoped semiconductor material 11 filled in a second trench of the pair byno more than 10%. In an embodiment, the variation can be even smallerthan 10%, such as 8%, smaller than 6%, or even smaller than 6%, such as4%. This variation may even be smaller than 3%, or even smaller than 2%.

For example, a volume integral of the dopant concentration of the dopedsemiconductor material 11 filled in any one of the trenches does notdeviate by more than 10% from an average value of the volume integralsof the dopant concentration of the doped semiconductor material filledin each of the trenches 10. In an embodiment, the deviation can be evensmaller than 10%, such as 8%, smaller than 6%, or even smaller than 6%,such as 4%. Due to this low variation between the volume integrals, thetransistor cells of the semiconductor wafer 1 may exhibit acomparatively homogeneous blocking voltage.

For example, the volume integral is determined along the entire width ofeach trench in the first lateral direction X, along the entire length inthe second lateral direction Y and along the entire depth in thevertical extension direction Z. Thus, the variation of the volumeintegrals can be determined along the first lateral direction X. Anexemplary distribution of the volume integrals is schematicallyillustrated by FIG. 4. Accordingly, in an example, the volume integralof the dopant concentration of trench 10 a may be slightly above theaverage dopant concentration illustrated by the dashed line 19. Thevolume integral of the dopant concentration of trench 10 b may beslightly below the average 19 and so on. For example, the variation thevolume integrals between the respective trenches 10 along the firstlateral direction X may be expressed by a scalar function.

In the following, embodiments of a method of processing a semiconductorwafer and embodiments of a semiconductor wafer processing system will bedescribed. For example, according to an embodiment, the semiconductorwafer 1 described above with respect to FIG. 1 and FIG. 2C can beproduced by means of the method or by means of the semiconductor waferprocessing system.

FIG. 2A-C schematically illustrate sections of vertical cross-sectionsof a semiconductor wafer 1 during some steps of a method of processingsuch semiconductor wafer 1 according to one or more embodiments. FIG. 3schematically illustrates a block diagram of components of asemiconductor wafer processing system 3 according to one or moreembodiments. In the following, it will be referred to both FIG. 2A-C andto FIG. 3.

For example, the method of processing the semiconductor wafer 1 mayinclude producing trenches 10 in the semiconductor wafer 1, wherein thetrenches 10 can be arranged next to each other along the first lateraldirection X. Each trench may further extend along the second lateraldirection Y and into the semiconductor wafer 1 along the verticalextension direction Z. For example, such trench production can becarried out by a trench production apparatus 31 (cf. FIG. 3) of thesemiconductor wafer processing system 3.

For example, the trenches 10 are produced such that all trenches 10exhibit the same total extension along the vertical extension directionZ. In other words, the trenches 10 may all exhibit approximately thesame trench depth. Further, the trenches 10 may each exhibitapproximately the same total extension along the second lateraldirection Y. In other words, the trenches 10 may all exhibitapproximately the same trench length. The distance (also referred to as“pitch”) along the first lateral direction X between every two adjacenttrenches of the trenches 10 may amount to less than 10 μm, to less than3 μm or even to less than 1 μm.

The method of processing the semiconductor wafer may further includeepitaxially filling the trenches 10 of the semiconductor wafer 1 with adoped semiconductor material 11. For example, epitaxially filling thetrenches 10 with the doped semiconductor material can be carried out bya trench filling apparatus 32 of the semiconductor wafer processingsystem 3. As already explained above, the doped semiconductor material11 may exhibit a band gap greater than the band gap of silicon, forexample a band gap greater than 2 eV. For example, the dopedsemiconductor material 11 is doped silicon carbide (SiC).

The method of processing the semiconductor wafer 1 may further comprisethe step of determining a parameter that is indicative of at least oneof a variation of dopant concentrations of the semiconductor material 11along the first lateral direction X that is to be expected when carryingout the epitaxially filling and a deviation of an expected average ofthe dopant concentrations from a predetermined nominal value.

Thus, the parameter may express an expected variation of the dopantconcentrations along the first lateral direction X. For example, asalready explained with respect to FIG. 4, such parameter may include ascalar function that expresses the expected variation of dopantconcentrations between the respective trenches 10 along at least thefirst lateral direction X. Or, the parameter may simply express that theexpected average dopant concentration is above or below thepredetermined nominal value, e.g., by a factor of 15% or more than 15%.

In an embodiment, the expected average dopant concentration is theexpected average over all trenches 10 or over at least some of thetrenches 10, such as every second of the trenches 10. The predeterminednominal value can be, e.g., a desired value of the dopant concentrationthat shall be present within each of the trenches 10.

For example, determining the parameter may include operating thesemiconductor wafer processing system 3 as follows: In a first step, thetrench production apparatus 31 of the system 3 produces trenches withinat least one test wafer (not illustrated) and the trench fillingapparatus 32 epitaxially fills the trenches of the at least one testwafer with the doped semiconductor material 11. In a next step, a dopantconcentration of the doped semiconductor material 11 in at least two ofthe trenches of the at least one test wafer is determined. Suchdetermining of the dopant concentration may comprise a correspondingmeasuring step and/or a corresponding sampling step, wherein differentsampling techniques may be applied, such as static sampling, adaptivesampling, and/or dynamic sampling. The type of sampling may further varydepending on the direction (X, Y or Z direction). Further, it shall beunderstood that, in accordance with an embodiment, a dopantconcentration of the doped semiconductor material 11 can also bemeasured in each of the trenches of the at least one test wafer and/orin at least some trenches of at least two test wafers and so on. Afterthe dopant concentration of the doped semiconductor material 11 has beendetermined, the parameter can be calculated in dependence of thedetermined dopant concentrations.

After the at least one test wafer has been processed, subsequentprocessing steps for processing the semiconductor wafer 1 can be carriedout by means of the semiconductor wafer processing system 3. Forexample, the parameter is determined before carrying out the step ofepitaxially filling the trenches 10 of the semiconductor wafer 1, oreven before the trenches 10 are produced within the semiconductor wafer1.

In accordance with an embodiment, the at least one subsequent processingstep is carried out in dependence of the determined parameter. Forexample, the semiconductor wafer processing system 3 further comprises acontroller 34 that is operatively coupled to at least one of the trenchproduction apparatus 31 and the trench filling apparatus 32. Thecontroller 34 may be configured to control at least one of the trenchproduction apparatus 31 and the trench filling apparatus 32 independence of the parameter. For example, the controller 34 implements afeed-forward-control based on that parameter for controlling at leastone of the trench production apparatus 31 and the trench fillingapparatus 32.

For example, in order to determine the parameter, the semiconductorwafer processing system 3 may comprise a determination unit 33 that isconfigured to determine the dopant concentration of the dopedsemiconductor material 11 within at least the two of the trenches 10.The controller 34 may be operatively coupled to the determination unit33 and may be configured to calculate the parameter in dependence of thedetermined dopant concentrations. For example, the determination unit 33may be configured to measure a dopant concentration within the trenchesof the semiconductor wafer 1 or, respectively, of the semiconductor testwafer mentioned above. Further, the determination unit 33 may beconfigured to carry out the sampling, i.e., a static sampling, anadaptive sampling and/or dynamic sampling in order to determine thedopant concentrations such that the parameter can be calculated. In anembodiment, the determination unit 33 is configured to determine thedopant concentration by carrying out a capacitance-voltage-measurement(C-V-measurement). For example, such capacitance-voltage-measurement canbe implemented at or along a sawing street (also referred to as “dicingline” or “dicing street” or “curf”; not illustrated) of thesemiconductor wafer. Alternatively or additionally, the determinationunit 33 may comprise a mercury prober (not illustrated) for measuringthe dopant concentration. For example, the latter kind of measurementcan be implemented within the active region 15 of the semiconductorwafer. Further, the determination unit 33 may be configured for beingarranged within a semiconductor wafer test field, e.g., at a position ofa semiconductor wafer production facility. The measurement of the dopantconcentration by the determination unit 33 can be implemented before thesemiconductor wafer is cut. As explained above, the active region 15 mayinclude a number of transistor cells (not illustrated in the figures)that are configured to carry a load current by means of thesemiconductor drift region 13 of the semiconductor wafer. Each of thetransistor cells may comprise at least one gate electrode, which can be,e.g., realized as a trench gate electrode extending into thesemiconductor drift region 13 or, respectively, as a planar gateelectrode being arranged above the semiconductor drift region 13. Thus,the measurements to be carried out by the determination unit 33 can beapplied to at least one of a semiconductor wafer exhibiting a planargate structure and a semiconductor wafer exhibiting a trench gatestructure.

In accordance with an embodiment, the step of epitaxially filling thetrenches 10 with the doped semiconductor material 11 is carried out at aprocessing temperature greater than 1400° C. Such processing temperaturecan be adequate for semiconductor materials exhibiting a band gapgreater than the band gap of silicon. For example, the processingtemperature can be greater than 1500° C., or greater than 1700° C.

In the following, some examples of subsequent processing steps shall bedescribed.

In accordance with an embodiment, the method may comprise providing aplurality of masks (not illustrated), wherein each mask exhibits aunique trench width design. That is to say: The trench width designs ofthe plurality of masks each differ from each other. For example, a firstof the plurality of masks exhibits a trench width design that defines awidth of 3.5 μm for each trench along the first lateral direction X. Asecond of the plurality of masks may exhibit a trench width design thatdefines a trench width along the first lateral direction X of 1 μm.Further, another trench of the plurality of masks may exhibit a trenchwidth design, wherein the width of the trenches may differ along thefirst lateral direction X. The at least one subsequent processing stepmay further comprise: Choosing one of the plurality of masks independence of the determined parameter and producing the trenches 10 andthe semiconductor wafer 1 by using the chosen mask. For example, themask that has been chosen in dependence of the determined parameter mayexhibit such a trench width design that compensates for the expectedvariation of the dopant concentrations so as to reduce the variation andso as to achieve a more homogeneous distribution of the dopantconcentration along the first lateral direction X. In an embodiment, thetrench production apparatus 31 may be configured to store such pluralityof masks within corresponding storage means (not illustrated). Thecontroller 34 may be configured for controlling the trench productionapparatus 31 such that trench production apparatus 31 chooses one of theplurality of masks in dependence of the parameter and uses the chosenmask for carrying out the trench production step.

In accordance with another embodiment, the method may include depositinga hard mask material on the semiconductor wafer 1 for producing a hardmask 12. Such hard mask 12 is schematically and exemplary illustrated inFIG. 2A. In a next step, the hard mask 12 may be structured, wherein thestructuring may include creating openings 121 a to 121 e in the hardmask 12, and wherein the openings 121 a to 121 e may be arranged next toeach other along the first lateral direction X and exhibit a respectivewidth Wa, . . . , We. For example, the structuring is carried out suchthat the widths Wa to We differ from each other in dependence of thedetermined parameter. For example, the variation of the widths Wa to Weis such that the volume integral of the dopant concentration of thedoped semiconductor material 11 to be filled within the trenches 10varies less than predicted by the parameter. In an embodiment, thetrench production apparatus 31 is configured to carry out suchdepositing and such structuring.

For example, the widths Wa to We are in each within the range of 0.5 μmto 5 μm.

In a next step, the trenches 10 may be created underneath the openings121 a to 121 e. Thus, in accordance with the embodiment described above,the parameter that expresses the expected variation may influence thestep of producing the trenches 10. As already indicated above, the stepof producing the trenches 10, including, e.g., the step of depositingthe hard mask material and the step of structuring of the hard mask, canbe carried out by means of the trench production apparatus 31 of thesystem 3. After the trenches 10 have been produced in dependence of theparameter, the trenches 10 may be epitaxially filled with the dopedsemiconductor material 11, wherein the latter step can be carried out,e.g., by means of the filling apparatus 32 of the system 3.

In accordance with an embodiment, the structuring of the hard mask 12may include controlling a wet etch process in dependence of thedetermined parameter. For example, the trench production apparatus 31 isconfigured to carry out such wet etch process and the controller 34 canbe configured to control the trench production apparatus 31, such as theimplementation of the wet etch process, in dependence of the determinedparameter.

In accordance with another embodiment, the step of structuring the mask12 may include controlling an exposure focus of an exposure unit independence of the parameter. For example, the trench productionapparatus 31 of the semiconductor wafer processing system 3 may comprisesuch exposure unit, which is schematically illustrated in FIG. 3 andidentified with reference sign 311. For example, the exposure unit 311is configured to be set selectively in one of an out-of-focus-mode andan in-focus-mode. If the exposure unit 311 is in the out-of-focus mode,the width of the hard mask 12, e.g., the width Wa, may be comparativelylarge, whereas, if the exposure unit 311 is in the in-focus mode, thewidth of an opening of the hard mask 12 can be comparatively small.Thus, by controlling an exposure focus of the exposure unit 311, it canbe possible to structure a hard mask 12 such that the openings 121 a to121 e of the hard mask 12 exhibit a respective width that differ fromeach other. The controlling of the exposure focus can be carried out independence of the parameter, e.g., such that the variation of the volumeintegral of the doped semiconductor material filled in the trenches 10is reduced as compared to the predicted variation expressed by theparameter.

In accordance with a yet further embodiment, the at least one subsequentprocessing step of the method may comprise the step of creating thetrenches 10 by carrying out an etch processing step, wherein the etchprocessing step can be controlled in dependence of the parameter. Forexample, the trench production apparatus 31 of the system 3 can beconfigured to carry out such etch processing step. The controller 34 canbe configured to control the implementation of the etch processing stepin dependence of the parameter. For example, a variation of the trenchwidth Wa to We can be achieved by adapting one or more of trench etchparameters according to which the etch processing step is carried out.For example, a plasma power, a plasma density, a gas flow rate, and/or agas composition are trench parameters that may be varied, in accordancewith an embodiment, in dependence of the determined parameter indicativeof the expected variation of the dopant concentration. For example, byadapting the at least one such trench etch parameters, a lateralvariation from an isotropic to an anisotropic etch rate can becontrolled. In an embodiment, a ratio between chemical (anisotropic)etch components and physical (isotropic) etch components is controlledby adapting gas parameters, e.g., by adapting at least one of a carriergas (e.g., helium (He) and/or argon (Ar)), the ratio between reactivecomponents (e.g., fluorocarbon (CF4), fluoroform (CFH3),nitrogen-fluorine (NF3), sulfur hexafluoride (SF₆), and/or oxygen (O₂))and the carrier gas, and the gas pressure. Further, adapting theseparameters may also allow for controlling the plasma density, e.g., theplasma density along a radial direction, i.e., in a directionsubstantially perpendicular to a plasma radiation direction.

In accordance with yet a further embodiment, the at least one subsequentprocessing step of the method may further comprise a partial filling ofat least some of the trenches 10 with a substantially undopedsemiconductor material 19 (cf. FIG. 2B). For example, the partialfilling of at least some of the trenches 10 with the substantiallyundoped semiconductor material 19 is carried out by means of the trenchfilling apparatus 31 of the semiconductor wafer processing system 3. Forexample, a thickness Ta, Tb of the substantially undoped semiconductormaterial 19 within the at least some trenches 10 a, 10 b can be adjustedin dependence of the determined parameter. Such optional method step isschematically and exemplary illustrated in FIG. 2B. Accordingly, thethickness Ta, Tb of the substantially undoped semiconductor material 19can be varied along the first lateral direction X. For example, thewidth Ta of the substantially undoped semiconductor material 19 that ispartially filled in the trench 10 a may be smaller than the thickness Tbof the substantially undoped semiconductor material 19 that is partiallyfilled in the adjacent trench 10 b. For example, by adjusting thethickness of the substantially undoped semiconductor material 19, thevolume of the remaining interior region of the respective trenches 10 a,10 b can be adjusted.

For example, the substantially undoped semiconductor material 19comprises at least one of silicon (Si), polysilicon (poly-Si), apolytype of a semiconductor, such as 3C, 4H, 6H or 15R or anotherpolytype of silicon carbide (SiC).

For example, the substantially undoped semiconductor material 19 isdeposited in the at least some trenches 10 a, 10 b. When carrying outthe step of partially filling the at least some trenches 10 a, 10 b withthe substantially undoped semiconductor material 19, it can, inaccordance with an embodiment, be ensured that not the entire interiorsurface of the trenches 10 a and 10 b is covered with the substantiallyundoped semiconductor material 19, but that openings remain, e.g., at abottom regions of the trenches 10 a, 10 b. Thereby, it can be ensuredthat the doped semiconductor material 11 that is epitaxially filled inthe trenches 10 afterwards, is in contact with the semiconductor driftregion 13 and not entirely isolated from the semiconductor drift region13 by the substantially undoped semiconductor material 19, as it isschematically and exemplary illustrated in FIG. 2C.

In accordance with yet a further embodiment, the at least one subsequentprocessing step may comprise modifying, after epitaxially filling thetrenches 10 with the doped semiconductor material 11, the dopantconcentration of the doped semiconductor material 11 by carrying out animplantation processing step.

For example, the implantation processing step is controlled independence of the parameter. In an embodiment, the trench fillingapparatus 32 of the semiconductor wafer processing system 3 can beconfigured for carrying out the implantation processing step, and thecontroller 34 can be configured to control implementation of theimplantation processing step in dependence of the parameter. Forexample, the implantation processing step comprises implantingimplantation ions at sidewalls of the trenches 10 and/or at the trenchbottoms of the trenches 10. Depending on the type of the implantationions, a degree of compensation can be adjusted both in the n-loadedregion as well as in the p-loaded region. The implantation step can becarried out by means known in the art. Further, the implantation stepmay comprise a plasma doping (PLAD) and/or an etch-implant-etchsequence. For example, after the implantation step has been carried out,implantation ions being present at a trench bottom can be removed, e.g.by carrying out an anisotropic etch process step.

The embodiments schematically illustrated in FIG. 1 to FIG. 4 anddescribed above include the recognition that some methods of epitaxiallyfilling trenches can yield a lateral variation of the dopantconcentration in the range of 10%. Further, the variation from wafer towafer within a single lot can be even above 10%, and a variation fromwafer lot to wafer lot can be even above 15%. There may be situations inwhich it is desirable to reduce such variation of the dopantconcentrations. For example, a reduction of such lateral variation maybe desirable for compensation semiconductor devices (also referred to assuperjunction semiconductor devices or as CoolMOS™ semiconductordevices), such as SiC-based compensation semiconductor devices, inparticular regarding the dopant concentration of a doped semiconductormaterial filled within compensation trenches of the semiconductordevice. In accordance with embodiments described above, both thereplicability as well as a lateral homogeneity of the dopantconcentration of the doped semiconductor material filled within trenchesof a semiconductor wafer can be increased. Further, in accordance withthe embodiments described above, a blocking voltage of the semiconductordevices included in the semiconductor wafer can be increased withrespect to the total vertical extension of the semiconductor devices.

Further, in accordance with the embodiments described above, afeed-forward-control may be implemented when processing a semiconductorwafer. Such feed-forward-control may include determining the parameterthat is indicative of at least one of the variation of the dopantconcentrations of the doped semiconductor material along the firstlateral direction that is to be expected when carrying out theepitaxially filling and a deviation of an expected average of the dopantconcentrations from a predetermined nominal value. For example, afterthis parameter has been determined, trenches are produced within asubsequent semiconductor wafer and the trenches are epitaxially filledwith a doped semiconductor material, wherein at least one of the trenchproduction and the epitaxially filling is controlled in dependence ofthe determined parameter so as to reduce the expected variation of thedopant concentrations.

As described above, a semiconductor wafer that has been processed inaccordance with the principles described above can comprise a pluralityof transistor cells, wherein each of the transistor cells may exhibit acompensation structure. The compensation structure can be formed atleast by means of the trenches that have been produced within thesemiconductor wafer, e.g., within a semiconductor drift zone. Forexample, the semiconductor drift region is a weekly doped semiconductorregion, wherein a dopant concentration of the semiconductor drift regionis compensated by means of the doped semiconductor material that hasbeen filled into the produced trenches of the semiconductor wafer. Itshall be understood that in between two adjacent trenches of thetrenches 10, which have been mentioned above with respect to FIG. 1-4and which may be configured to be employed for compensation purposes,there may also be arranged one or more other trenches, e.g., trenchesthat used for other purposes than compensation, such as controlregarding turn-off and/or turn-on processes.

It shall be understood that the semiconductor wafer processing system 3as exemplarily described with respect to FIG. 3 can be a distributedsystem that comprises a plurality of semiconductor wafer processingequipment components. For example, the trench production apparatus 31may comprise means for producing the hard mask on the semiconductorwafer and/or means for choosing one of the plurality of pre-producedmasks and for positioning a chosen mask on top of the semiconductorwafer. Further, the trench production apparatus 31 may comprise meansfor etching a trench within the semiconductor wafer, means forstructuring a hard mask, e.g., by modifying an exposure focus of anexposure unit, means for carrying out an etch process, such as a wetetch process, a plasma etch process and/or further means for producingand modifying a trench that is known in the art. Accordingly, the trenchfilling apparatus 32 may also comprise a plurality of means for fillingthe trenches with a doped semiconductor material and/or for modifying adopant concentration of the doped semiconductor material. For example,the trench filling apparatus 32 comprises an epitaxy equipmentconfigured to carry out epitaxial processing steps, an implantation unitconfigured to carry out implantation processing steps and/or furthermeans configured to fill the trenches with a doped semiconductormaterial and/or for modifying a dopant concentration of the dopedsemiconductor material that are known in the art. Correspondingly, thedetermination unit 33 can comprise means configured to carry out ameasurement of a dopant concentration and/or configured to carry outsampling steps, such as static, adaptive and/or dynamic sampling stepsin order to determine the dopant concentration within at least some ofthe produced trenches. The controller 34 may comprise a processor anddata storage means operatively coupled to the processor and configuredto store a code that can be executed by the processor. For example, thecode may include instructions for controlling the trench productionapparatus 31, for controlling the trench filling apparatus 32 and/or forcontrolling the determination unit 33. The controller 34 can be coupledto each of the trench production apparatus 31, the trench fillingapparatus 32 and the determination unit 33. Such coupling can beimplemented, e.g., by means of wireless and/or hard-wired interfaces. Inan embodiment, the semiconductor processing system 3 is configured toautomatically determine the parameter by means of the determination unit33.

A possible application of the principles described above with respect tosome embodiments can include the following: As soon as a lot ofsemiconductor wafers is prepared for trench etching, the parameter isdetermined, e.g., by controlling the determination unit 33 by means ofthe controller 34 after having previously processed at least one testwafer. As explained above, the parameter can be indicative of at leastone of the variation of dopant concentrations of the doped semiconductormaterial along the first lateral direction X that is to be expected whencarrying out the epitaxial filling and the deviation of an expectedaverage of the dopant concentrations from a predetermined nominal value.After the parameter has been determined, the semiconductor waferprocessing system 3 can be blocked for a while. The parameter can beused for adapting the subsequent processing step, e.g., for determiningprocessing parameters of a plasma etch process to be carried out by thetrench production apparatus 31. As soon as the subsequent processingstep has been adapted in dependence of the parameter, blocking of thesemiconductor wafer processing system 3 can be released and productionand filling of the trenches within all semiconductor wafers of asemiconductor wafer lot can be implemented by carrying out thesubsequent processing step, e.g., by means of the trench productionapparatus 31 and the trench filling apparatus 32. For example, animplantation can be additionally carried out in order to compensate fora variation between a first semiconductor wafer lot and a secondsemiconductor wafer lot.

Features of further embodiments are defined in the dependent claims. Thefeatures of further embodiments and the features of the embodimentsdescribed above may be combined with each other for forming additionalembodiments, as long as the features are not explicitly described asbeing alternative to each other.

In the above, embodiments pertaining to semiconductor wafers and tomethods and systems for processing a semiconductor wafer were explained.For example, these semiconductor wafers are based on silicon (Si).Accordingly, a monocrystalline semiconductor region or layer, e.g., thesemiconductor regions 13 and 10 a to 10 e of exemplary embodiments, canbe a monocrystalline Si-region or Si-layer. In other embodiments,polycrystalline or amorphous silicon may be employed.

It should, however, be understood that the semiconductor regions 13 and10 a to 10 e can be made of any semiconductor material suitable formanufacturing a semiconductor device. Examples of such materialsinclude, without being limited thereto, elementary semiconductormaterials such as silicon (Si) or germanium (Ge), group IV compoundsemiconductor materials such as silicon carbide (SiC) or silicongermanium (SiGe), binary, ternary or quaternary III-V semiconductormaterials such as gallium nitride (GaN), gallium arsenide (GaAs),gallium phosphide (GaP), indium phosphide (InP), indium galliumphosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indiumnitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indiumnitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), andbinary or ternary II-VI semiconductor materials such as cadmiumtelluride (CdTe) and mercury cadmium telluride (HgCdTe) to name few. Theaforementioned semiconductor materials are also referred to as“homojunction semiconductor materials”. When combining two differentsemiconductor materials a heterojunction semiconductor material isformed. Examples of heterojunction semiconductor materials include,without being limited thereto, aluminum gallium nitride (AlGaN)-aluminumgallium indium nitride (AlGaInN), indium gallium nitride(InGaN)-aluminum gallium indium nitride (AlGaInN), indium galliumnitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride(AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminumgallium nitride (AlGaN), silicon-silicon carbide (SixC1-x) andsilicon-SiGe heterojunction semiconductor materials. For powersemiconductor devices applications currently mainly Si, SiC, GaAs andGaN materials are used.

Spatially relative terms such as “under”, “below”, “lower”, “over”,“upper” and the like, are used for ease of description to explain thepositioning of one element relative to a second element. These terms areintended to encompass different orientations of the respective device inaddition to different orientations than those depicted in the figures.Further, terms such as “first”, “second”, and the like, are also used todescribe various elements, regions, sections, etc. and are also notintended to be limiting. Like terms refer to like elements throughoutthe description.

As used herein, the terms “having”, “containing”, “including”,“comprising”, “exhibiting” and the like are open ended terms thatindicate the presence of stated elements or features, but do notpreclude additional elements or features. The articles “a”, “an” and“the” are intended to include the plural as well as the singular, unlessthe context clearly indicates otherwise.

With the above range of variations and applications in mind, it shouldbe understood that the present invention is not limited by the foregoingdescription, nor is it limited by the accompanying drawings. Instead,the present invention is limited only by the following claims and theirlegal equivalents.

The invention claimed is:
 1. A method of processing a semiconductorwafer, including epitaxially filling of trenches of the semiconductorwafer with a doped semiconductor material, wherein the trenches arearranged next to each other along a first lateral direction, the methodcomprising: determining an expected average of dopant concentrations ofthe doped semiconductor material of the trenches and a nominal value ofdopant concentrations of the doped semiconductor material of thetrenches; determining a parameter indicative of at least one of avariation of dopant concentrations of the doped semiconductor materialalong the first lateral direction (X) that is to be expected whencarrying out the epitaxially filling and a deviation of the expectedaverage of the dopant concentrations from the nominal value; andcarrying out at least one processing step in dependence of theparameter.
 2. The method of claim 1, wherein the doped semiconductormaterial exhibits a band gap greater than a band gap of silicon.
 3. Themethod of claim 1, wherein the step of epitaxially filling the trenchesis carried out at a processing temperature greater than 1400° C.
 4. Themethod of claim 1, wherein the parameter includes a scalar functionexpressing the variation of dopant concentrations between the respectivetrenches along at least the first lateral direction.
 5. The method ofclaim 1, wherein determining the parameter includes: operating asemiconductor wafer processing system by producing, with a trenchproduction apparatus of the system, trenches within at least one testwafer and by epitaxially filling, with a trench filling apparatus of thesystem, the trenches of the at least one test wafer with the dopedsemiconductor material; determining a dopant concentration of the dopedsemiconductor material in at least two of the trenches of the at leastone test wafer; and calculating the parameter in dependence of thedopant concentrations of the doped semiconductor material in at leasttwo of the trenches of the at least one test wafer.
 6. The method ofclaim 5, wherein the at least one processing step is carried out bymeans of the semiconductor wafer processing system for processing thesemiconductor wafer after having processed the at least one test wafer.7. The method of claim 1, including: providing a plurality of masks,wherein each mask exhibits a trench width design that is different fromthe design of each other mask; wherein the at least one processing stepcomprises: choosing one of the plurality of masks in dependence of theparameter; and producing the trenches in the semiconductor wafer byusing the chosen mask.
 8. The method of claim 1, wherein the at leastone processing step comprises: depositing a hard mask material on thesemiconductor wafer for forming a hard mask; structuring the hard mask,wherein the structuring includes creating openings in the hard mask, theopenings being arranged next to each other along the first lateraldirection and exhibiting a respective width that varies along the firstlateral direction in dependence of the parameter; and creating,underneath the openings, the trenches in the semiconductor wafer.
 9. Themethod of claim 8, wherein structuring the hard mask includescontrolling a wet etch process in dependence of the parameter.
 10. Themethod of claim 8, wherein structuring the mask includes controlling anexposure focus of an exposure unit of a semiconductor wafer processingsystem in dependence of the parameter.
 11. The method of claim 1,wherein the at least one processing step comprises creating the trenchesby carrying out an etch processing step, wherein the etch processingstep is controlled in dependence of the parameter.
 12. The method ofclaim 1, wherein the at least one processing step comprises partiallyfilling at least some of the trenches with a semiconductor material,wherein a thickness of the semiconductor material within the at leastsome trenches is adjusted in dependence of the parameter.
 13. The methodof claim 1, wherein the at least one processing step comprises:modifying, after epitaxially filling the trenches with the dopedsemiconductor material, the dopant concentration of the dopedsemiconductor material by carrying out an implantation processing step,wherein the implantation processing step is controlled in dependence ofthe parameter.
 14. A semiconductor wafer processing system forprocessing a semiconductor wafer, comprising: a trench productionapparatus configured to produce trenches in the semiconductor wafer, thetrenches being arranged next to each other along a first lateraldirection; a trench filling apparatus configured to epitaxially fill thetrenches with a doped semiconductor material; and a controlleroperatively coupled to at least one of the trench production apparatusand the trench filling apparatus, wherein the controller is configuredto control at least one of the trench production apparatus and thetrench filling apparatus in dependence of a parameter, the parameterbeing indicative of at least one of a variation of dopant concentrationsof the doped semiconductor material along the first lateral direction(X) that is to be expected when carrying out the epitaxially filling anda deviation of an expected average of the dopant concentrations from anominal value.
 15. The semiconductor wafer processing system of claim14, wherein the controller is configured to implement afeed-forward-control based on the parameter for controlling at least oneof the trench production apparatus and the trench filling apparatus. 16.The semiconductor wafer processing system of claim 14, furthercomprising a determination unit configured to determine a dopantconcentration of the doped semiconductor material within at least two ofthe trenches, wherein the controller is operatively coupled to thedetermination unit and configured to calculate the parameter independence of the dopant concentration.
 17. The semiconductor waferprocessing system of claim 16, wherein the controller is configured tocontrol the semiconductor wafer processing system such that thefollowing processing steps are carried out: with the trench productionapparatus, producing trenches in at least one test wafer, the trenchesbeing arranged next to each other along a first lateral direction; withthe trench filling apparatus, epitaxially filling the trenches of the atleast one test wafer with a doped semiconductor material; with thedetermination unit: determining a dopant concentration of the dopedsemiconductor material within at least two of the trenches of the atleast one test wafer; and processing the semiconductor wafer bycontrolling at least one of the trench production apparatus and thetrench filling apparatus based on the parameter that has been calculatedbased on the dopant concentration of the doped semiconductor materialthat has been filled into the trenches of the at least one test wafer.